This invention relates to a digital phase-lock loop (DPLL), and more particularly to a DPLL in which the transfer function of the loop is comprised of an estimator and a predictor of error.
A phase locked loop (PLL) is a feedback system that tracks the phase of a received quasi-periodic signal. A typical PLL structure is shown in FIG. 1. The difference between the received phase and a voltage controlled oscillator (VCO) phase is filtered and used to so adjust the VCO that the VCO phase tracks the received phase.
Designers of PLL's select a loop filter to meet performance requirements, usually specified in terms of bandwidth, gain margin, and dynamic errors. Design methods are well documented in the literature. Gardner, F. M., Phaselock Techniques, John Wiley and Sons, (1979). Best, R. E., Phase Locked Loops, Theory, Design and Applications, McGraw Hill, (1984). Viterbi, A. J., Principles of Coherent Communication, McGraw Hill (1966).
What is of interest here is a digital phase-lock loop (DPPL) characterized by constant loop update rates. For a discussion of DPLLs with variable loop update rate, see Gill, G. S., and Gupta, S. C., "First Order Discrete Phase Locked Loops with Applications to Demodulation of Angle Modulated Carrier", IEEE Trans. on Communications, June 1972; Weinberg, A. and Liu, B., "Discrete Time Analysis of Nonuniform Sampling First-and-Second-Order Digital Phase Locked Loops", IEEE Trans. on Communications, February 1974; Osborne, H. C., "Stability Analysis of Nth Power Digital Phase Locked Loop--Part I: First Order DPLL", IEEE Trans. on Communications, August 1980; Osborne, H. C., "Stability Analysis of Nth Power Digital Phase Locked Loop--Part II: Second and Third Order DPLLs", IEEE Trans. on Communications, August 1980. DPPLs with fixed update rate are often designed either by analogy to continuous time domain PLLs, or based on an optimality criterion.
Design by analogy to continuous domain PLLs, i.e., applying s-plane design rules by translation to the z-plane, suffers from two major disadvantages. The design is based on iteratively placing open-loop poles and zeroes at "well chosen" locations until satisfactory performance is achieved. Such locations are selected based on design experience rather than on well established set of rules. Also, the design does not accound for the transport delay in the digital loop, caused by hardware delays and loop filter computations. This delay is either "tolerated," i.e., the degradation due to the delay is analyzed and found to be acceptable or "compensated" by the equivalent of a lead-lag network. This design procedure is usually acceptable only when the loop update rate is very high compared to the loop bandwidth.
Design based on an optimality criterion as discussed, for example, by Gupta, S. C., "On Optimum Digital Phase-Locked Loops", IEEE Transactions on Communications Technology, Vol 16, No. 2, April 1968, attempts to optimize a concise performance measure, such as a weighted sum of integrated transient response, gain margin, and noise variance. For some cases, analytical expressions for the performance measure can be obtained, and closed-form expressions for loop filters defined. Disadvantages are that the loop filter form (e.g., order of loop) is not defined apriori, but rather is a result of the optimization procedure, and that the design procedure is complex.
The estimator-predictor approach described in this application offers an alternate design for DPLLs. The DPLL design presented here is shown to be equivalent to an estimator followed by a predictor compensating for the transport lag. The estimator incorporates past measurements of phase into a state vector estimate, consisting of phase, frequency, and perhaps higher derivatives. Selection of an estimator can utilize the base resources available in linear optimal estimation theory.